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tfs757-764hg hipertfs family www.powerint.com february 2011 combined two-switch forward and flyback power supply controllers with integrated high voltage mosfets ? hd dc input main output auxiliary/standby output rtn g s hipertfs vddh l fb fb en en bp dsb en fb control, gate drivers, level shift r d hs pi-6200-102910 two-switch forward transformer flyback transformer figure 1. simplifed schematic of two-switch forward and flyback converter. key benefts ? single chip solution for two-switch forward main and fyback standby ? high integration allows smaller form factor and higher power density designs ? incorporates control, gate drivers, and three power mosfets ? level shift technology eliminates need for pulse transformer ? protection features include: uv, ov, otp, ocp, and scp ? transformer reset control ? prevents transformer saturation under all conditions ? allows >50% duty cycle operation ? reduces primary side rms currents and conduction losses ? standby supply provides built-in overload power compensation ? up to 434 w total output power in a highly compact package ? up to 550 w peak ? high effciency solution easily enables design to meet stringent effciency specifcations ? >90% effciency at full load ? no-load regulation and low losses at light-load ? simple clip mounting to heat sink without need for insulation pad ? halogen free and rohs compliant applications ? pc ? printer ? lcd tv ? video game consoles ? high-power adapters ? industrial and appliance high-power adapters output power table product two-switched forward 380 v flyback 100 v - 400 v continuous (25 c) continuous (50 c) peak (50 c) 50 c tfs757hg 193 w 163 w 228 w 20 w TFS758HG 236 w 200 w 278 w 20 w tfs759hg 280 w 235 w 309 w 20 w tfs760hg 305 w 258 w 358 w 20 w tfs761hg 326 w 276 w 383 w 20 w tfs762hg 360 w 304 w 407 w 20 w tfs763hg 388 w 327 w 455 w 20 w tfs764hg 414 w 344 w 530 w 20 w table 1. output power table (see notes on page 13).
rev. c 02/11 2 tfs757-764hg www.powerint.com section list description .................................................................................................................................................................. 3 product highlights ...................................................................................................................................................... 3 pin functional description ......................................................................................................................................... 5 pin confguration ...................................................................................................................................................... 5 functional block diagram ..................................................................................................................................... 6-7 functional description ............................................................................................................................................... 8 output power table ............................................................................................................................................... 13 design, assembly, and layout considerations .................................................................................................... 14 application example ................................................................................................................................................. 20 absolute maximum ratings ..................................................................................................................................... 23 parameter table ..................................................................................................................................................... 23 typical performance characteristics ................................................................................................................. 29-33 package details ........................................................................................................................................................ 34 part ordering information ......................................................................................................................................... 35 part marking information ......................................................................................................................................... 35
rev. c 02/11 3 tfs757-764hg www.powerint.com description the hipertfs device family members incorporate both a high-power two-switch-forward converter and a mid-power fyback (standby) converter into a single, low-profle esip? power package. the single chip solution provides the controllers for the two-switch-forward and fyback converters, high- and low-side drivers, all three of the high-voltage power mosfets, and eliminates the converters need for costly external pulse transformers. the device is ideal for high power applications that require both a main power converter (two-switch forward) up to 414 w, and standby converter (fyback) up to 20 w. hipertfs includes power integrations standard set of comprehen- sive protection features, such as integrated soft-start, fault and over-load protection, and hysteretic thermal shutdown. hipertfs utilizes advanced power packaging technology that simplifes the complexity of two-switch forward layout, mounting and thermal management, while providing very high power capabilities in a single compact package. the devices operate over a wide input voltage range, and can be used following a power-factor correction stage such as hiperpfs. two-switch-forward power converters are often selected for applications demanding cost-effective effciency, fast transient response, and accurate tolerance to line voltage fuctuation. the two-switch-forward controller incorporated into hipertfs devices improves on the classic topology by allowing operation considerably above 60% duty cycle. this improvement reduces rms currents conduction losses, minimizes the size and cost of the bulk capacitor, and minimizes output diode voltage ratings. the advanced design also includes transformer fux reset control (saturation protection) and charge-recovery switching of the high-side mosfet, which reduces switching losses. this combination of innovations yields an extremely effcient power supply with smaller mosfets, fewer passives and discrete components, and a lower-cost transformer. hipertfss fyback standby controller and mosfet solution is based on the highly popular tinyswitch? technology used in billions of power converter ics due to its simplicity of operation, light load effciency, and rugged, reliable, performance. this fyback converter can provide up to 20 w of output power and the built in overload power compensation reduces component design margin. product highlights protected two-switch forward and flyback combination solution ? incorporates three high-voltage power mosfets, main and standby controllers, and gate drivers ? level shift technology eliminates need for pulse transformer ? programmable line undervoltage (uv) detection prevents turn-off glitches ? programmable line overvoltage (ov) detection; latching and non-latching ? accurate hysteretic thermal shutdown (otp) ? accurate selectable current limit (main and standby) ? output over-current protection (ocp) ? fully integrated soft-start for minimum start-up stress ? simple fast ac reset ? reduced emi ? synchronized 66 khz forward and 132 khz fyback converters ? frequency jitter ? eliminates up to 30 discrete components for higher reliability and lower cost asymmetrical two-switch forward reduces losses ? allows >50% duty cycle operation ? reduces primary side rms currents and conduction losses ? minimizes the size and cost of the bulk capacitor ? allows reduced capacitance or longer hold-up time ? allows lower voltage output diodes ? transformer reset control ? prevents transformer saturation under all conditions ? extends duty cycle to satisfy ac cycle drop out ride through ? duty cycle soft-start with 115% current limit boost ? satisfes 2 ms ~ 20 ms start-up with large capacitance at output ? output short circuit protection (scp) with auto-restart ? remote on/off function ? voltage mode controller with current limit 20 w flyback with selectable power limit ? tinyswitch-iii based converter ? selectable power limit (10 w, 12.5 w, 15 w, or 20 w) ? built-in overload power compensation ? flat overload power vs. input voltage ? reduces component stress during overload conditions ? reduces required design margin for transformer and output diode ? output overvoltage (ov) protection with fast ac reset ? latching, non-latching, or auto-restart ? auto-restart advanced package for high power applications ? 434 w output power capability in a highly compact package ? up to 550 w peak ? simple clip mounting to heat sink ? can be directly connected to heat sink without insulation pad ? provides thermal impedance equivalent to a to-220 ? heat slug connected to ground potential for low emi ? staggered pin arrangement for simple routing of board traces and high-voltage creepage requirements ? single power package for two power converters reduces assembly costs layout size
rev. c 02/11 4 tfs757-764hg www.powerint.com table 2. summary of differences between hipertfs and other typical high power supplies. function typical two-switch forward hipertfs advantages of hipertfs nominal duty cycle 33% 45% wider duty cycle reduces rms switch currents by 17%. reduces r ds(on) losses by 31% maximum duty cycle <50% 63% switch current (rms) 100% 83% output catch diode v o + v d /d max v o + v d /d max lower losses. wider d max lowers catch diode rating by (1-(50%/63%)) = 21% reduction in catch diode voltage rating clamp voltage reset diodes from zero to v in reset from zero to (v in + 130) with fast/slow diode combination, allows charge recovery to limit high-side c oss loss thermal shutdown --- 118 c shutdown / 55 c hysteresis hipertfs provides integrated otp device protection current sense resistor 0.5 v drop (0.33 w at 300 w) sense resistor not required improved effciency. mosfet r ds(on) sense eliminated need for sense resistor high-side drive requires gate-drive transformer (high cost) built in high-side drive lower cost; component elimination. removes high-cost gate-drive transformer (ee10 or toroid) component count higher lower saves up to 50 components, depending on specifcation. tinyswitch overload power compensation vs. input voltage --- built-in compensation safer design; easier to design power supply. flattens overload output power over line voltages package creepage to-220 = 1.17 mm esip16/12 = 2.3 mm/ 3.3 mm hipertfs meets functional safety spacing at package pins package assembly 2 to-220 package, 2 sil (insulation) 1 package no sil (insulation) pad required
rev. c 02/11 5 tfs757-764hg www.powerint.com pin functional description main drain (d) pin drain of the low-side mosfet transistor forward converter. standby drain (dsb) pin drain of the mosfet of standby power supply. ground (g) pin this pin gives a signal current path to the substrate of the low-side controller. this pin is provided to allow a separate kelvin connection to the substrate of the low-side controller to eliminate inductive voltages that might be developed by high switching currents in the source pin. the ground pin is not intended to carrier high currents, instead it is intended as a voltage-reference connection only. source (s) pin source pin that is common to both the standby and main supplies. reset (r) pin this pin provides information to limit the maximum duty cycle as a function of the current fed into the reset pin during the off-time of the main converter mosfet. this pin can also be pulled up to bypass to signal remote on/off of the main converter only. enable (en) pin this is the enable pin for the standby controller. prior to the start-up a resistor connected from enable to bypass, can be detected to select one of several internal current limits. line-sense (l) pin this pin provides input bulk voltage line-sense function. this information is used by the undervoltage and overvoltage detection circuits for both main and standby. the pin can also be pulled up to bypass or be pulled down to source to implement a remote on/off of both standby and main supplies simultaneously. the line-sense pin works in conjunction with the reset pin to implement a duty-cycle limit function. also the line-sense pin compensates the value of standby current limit so as to fatten the output overload response as a function of input voltage. feedback (fb) pin this pin provides feedback for the main two transistor forward converter. an increase in current sink from feedback pin to ground, will lead to a reduction in operating duty cycle. this pin also selects the main device current limit at start-up (in a similar manner to enable pin). bypass (bp) pin this is the decoupled operating voltage pin for the low-side controller. at start-up the bypass capacitor is charged from an internal device current source. during normal operation the capacitor voltage is maintained by drawing current from the low-side bias winding on the standby power supply. this pin is also used to implement remote on/off for the main controller. this is done by driving extra current into the bypass pin when we want to turn-on the main controller. the bypass pin also implements a latch-off function to disable standby and main when the bp pin current exceeds latching threshold. latch is reset when line-sense pin falls below uv (off) standby threshold. high-side operating voltage (vddh) pin this is the high-side bias (vdd) of approximately 11.5 v. this voltage is maintained with current from a high-side bias winding on the main transformer and/or from a bootstrap diode from the low-side standby bias supply. high-side source (hs) pin source pin of the high-side mosfet. high-side drain (hd) pin drain pin of the high-side mosfet. this mosfet is foating with respect to low-side source and ground. figure 2. pin confguration. pi-5290-110510 16 d dsb g s r en hd hd hs s s l fb hs hd vddh bp 14 13 10 11 9 1 3 5 6 7 8 h package (esip-16/12) exposed pad (backside) internally connected to source pin (see esip-16b package drawing) exposed metal (on edge) internally connected
rev. c 02/11 6 tfs757-764hg www.powerint.com pi-5263-021511 pwm comparator pwm input thermal sd controlled turn-on gate driver current limit comparator source (s) s r q - + bypass (bp) line-sense (l) reset (r) feedback (fb) and main current limit select stop hsd1 hsd2 fault present lv saw d 2max clk2 main remote-on + - leading edge blanking r l duty cycle limit d max gate clk on drain (d) v bg line sense lv power on i limit select vi limit dss soft-start pwm input remote off remote off gate hs 3 v+vt figure 3. functional block diagram for two-switch forward converter. high-side operating voltage (vddh) hsd1 hsd2 12 v 11.1 v 9.9 v high-side drain (hd) high-side source (hs) vddh undervoltage pi-5516-060410 + s r q discriminator
rev. c 02/11 7 tfs757-764hg www.powerint.com figure 4. functional block diagram for flyback/standby converter. pi-5264-020510 clock clk2 5.7 v 4.7 v source (s) s r q dc max d 2max saw bypass (bp) + - v i limit fault present current limit comparator enable leading edge blanking thermal shutdown + - standby drain (dsb) bypass pin under-voltage lv (line voltage) saw d 2max clk2 fault present oscillator thermal sd 1.0 v + v t enable (en) and standby curren limit select q 115 a reset auto- restart counter jitter 1.0 v 6.0 v enable pull up resistor select and current limit state machine main remote on/ ovp latch off v in i limit adjust main remote on regulator 5.7 v
rev. c 02/11 8 tfs757-764hg www.powerint.com functional description the hipertfs contains two switch-mode power supply controllers and associated low-side mosfets along with high-side driver and high-side mosfet. ? the hipertfs two-switch forward includes a controller along with low-side power mosfet, high-side power mosfet and high-side driver. this device operates in voltage mode (linear duty-cycle control) at fxed frequency (exactly half the operat - ing frequency of the standby controller). the control converts a current input (feedback pin), to a duty-cycle at the open drain mosfet main drain pin decreasing duty-cycle with increasing sourced current from the feedback pin. ? the hipertfs fyback includes a controller and power mosfet which is based on tinyswitch-iii. this device operates in multi-level on/off current limit control mode. the open drain mosfet (standby drain pin) is turned on when the sourced current from the enable pin is below the threshold and switching is disabled when the enable pin current is above the threshold. in addition to the basic features, such as the high-voltage start-up, the cycle-by-cycle current limiting, loop compensation circuitry, auto-restart and thermal shutdown, the hipertfs main controller incorporates many additional functions that reduce system cost, increase power supply performance and design fexibility. main converter general introduction the main converter for the hipertfs, is a two-switch forward converter (although the hipertfs could be used with other two-switch topologies). this topology involves a low-side and high-side power mosfet, both of which are switched at the same time. in the case of the hipertfs, the low-side mosfet is a 725 v mosfet (with the substrate connected to the source pin). the high-side mosfet is a 530 v mosfet (with the substrate connected to the high-side drain (hd) pin). as such the substrate of both low-side and high-side mosfets are tied to quiet circuit nodes (0 v and v in respectively), meaning that both mosfets have electrically quiet substrates C good for emi. the low-side mosfet has a very low c oss capacitance and thus can be hard-switched without performance penalty. due to the external clamp confguration it is possible to substantially soft-switch the high-side mosfet at high-loads (thus eliminating a large proportion of high-side capacitive switching loss) and improving effciency. the higher breakdown voltage on the low-side mosfet allows the transformer reset voltage to exceed the input voltage, and thus allow operation at duty cycles greater than 50%. higher duty cycle operation leads to lower rms switch currents and also lower output diode voltage-rating, both of which contribute to improved effciency. the hipertfs also contains a high-side driver to control the high-side mosfet. this internal high-side driver eliminates the need for a gate-driver transformer, an expensive component that is required for many other two-switch forward circuits. main start-up operation once the fyback (standby) converter is up and running, the main converter can be enabled by two functions. the frst condition is that the bypass pin remote-on current must exceed the remote-on threshold (i bp(on) ), provided by an external remote on/off circuit. this current threshold has a hysteresis to prevent noise interference. once the bypass remote-on has been achieved, the hipertfs also requires that the line- sense pin current exceeds the uv main-on (i l(ma-uvon) ), which corresponds to approximately 315 vdc input voltage when using a 4 m w line-sense pin resistor. once this line-sense pin threshold has been achieved the hipertfs will enter a 12 ms pre-charge period (t d(ch) ) to allow the pfc-boost stage to reach regulation before the main applies a load to the bulk-capacitor. also during this pre-charge period the high-side driver is charged via the boot-strap diode from the low-side auxiliary voltage, and is charged when the main low-side mosfet turns figure 5. switching frequency jitter (idealized v drain waveforms). pi-4530-041 10 7 f osc - 4 ms ti me switching frequency v drain f osc + figure 6. supply start-up sequence by remote on. v in standby output main output 12 ms 385 v main primary current remote on 12 ms 32 ms t t t t t pi-5619a-102710 100% i lim 115% i lim
rev. c 02/11 9 tfs757-764hg www.powerint.com on, while the main high-side mosfet is held off. by the end of the pre-charge period, the pfc-boost voltage should be at or above the nominal boost voltage. the hipertfs begins switching, going through the soft-start period (t ss ). during the soft-start period the maximum duty cycle starts at 30% and is ramped during a 12 ms period to the maximum. the ramped duty cycle controls the rise slew rate of the output during start-up, allowing well controlled start-up and also facilitates a smooth transition when the control loop takes over regulation towards the end of soft-start. also during a 32 ms period (starting at the beginning of soft-start), the main current limit is boosted to 115% of the nominal selected main current. this allows the main to start-up within the required period for the application (typically < 20 ms for pc main applications), when there is a substantial capacitive load on the output. after the soft-start period, the current limit returns to 100% of the nominal selected current limit. main converter control feedback (fb) pin operation the feedback pin is the input for control loop feedback from the main control loop. during normal operation the feedback pin is used to provide duty cycle control for the main converter. the system output voltage is detected and converted into a feedback current. the main converter duty cycle will reduce as more current is sourced from the feedback pin, reaching zero duty cycle at approximately 2.1 ma. the nominal voltage of the feedback pin is maintained at approximately 3.5 v. an internal pole on the feedback pin is set to approximately 12 khz, in order to facilitate optimal control loop response. the maximum duty cycle of the main converter is defned by the line-sense pin and reset pin behavior and is a dynamically calculated value according to cycle-by-cycle conditions on the line-sense pin and reset pin. main high-side driver the high-side driver is a device that is electrically foating at the potential of the high-side mosfet source (hs) pin. this device provides gate-drive for the high-side main mosfet. the low-side main and high-side main mosfets switch simul- taneously. the high-side driver has a high-side operating voltage supply pin. external circuitry provides a current source into this high-side operating voltage pin. the high-side operating voltage has an internal 12 v shunt-regulator. the device consumes approximately 2 ma when driving the high-side mosfet. the high-side operating voltage pin has an undervoltage lock-out threshold, to prevent gate-drive when the supply voltage drops below a safe threshold. at power-up the high-side driver remains in the off-state, until the high-side operating voltage pin is charged above 10.5 v, at which point the high-side driver becomes active. the high-side driver is initially charged via a boot-strap diode connected via a diode to the high-side operating voltage pin from the low-side standby auxiliary supply (approximately 12 v). during start-up the high-side mosfet remains off, but the low-side mosfet is turned on for a period of 14 ms to allow pre-charge of the high-side operating voltage to 12 v. after this period, the high- side operating voltage is supplied by a forward-winding coupled to the main transformer. this foating winding provides energy every time the main converter switches one cycle. the operating power for high-side operating voltage can also be provided from a foating winding on the standby supply. however this would continue delivering power even when the main converter is in remote-off, and thus is considered undesirable from a standby light-load effciency point of view. once the high-side driver is operating it receives level-shifted drive commands from the low-side device. these drive commands cause both turn-on and turn-off drive of the high-side main mosfet simultaneously with that of the low-side main mosfet. the high-side driver also contains a thermal shutdown on-chip, but this is set to a temperature above the thermal shutdown temperature of the low-side device. thus the low-side will always shutdown frst. main converter maximum duty cycle the line-sense pin resistor converts the input voltage into an line-sense pin current signal. the reset pin resistor converts the reset voltage into an reset pin current signal. the line-sense pin and reset pin currents allow the hipertfs to determine a maximum duty cycle envelope on a cycle-by-cycle basis. this feature ensures suffcient time for transformer reset on a cycle-by-cycle basis and also protects against single-cycle transformer saturation and at high-input voltage by limiting the maximum duty cycle to prevent the transformer from reaching an unsafe fux density during the on-time period. both of these features allow the optimal performance to be obtained from the main transformer. the duty cycle limit is trimmed during production. the line-sense pin and reset pin are sampled just before the turn-on of the next main cycle. this is done to sample at a point when there is minimal noise in the system. due to the low current signal input to the line-sense pin and reset pin, care should be taken to prevent noise injection on these pins (see applications section layout guidelines for details). main on-chip current limit with external selection during start-up, the feedback pin and enable pin are both used to select internal current limits for the main and standby converters respectively. the detection period occurs at the initial start-up of the device, and before the main or standby mosfets start switching. this is done to minimize noise interference. figure 7. pwm duty cycle vs. control current. 63% 78% 0% 1 ma 2.1 ma duty (d) feedback pin current i fb i l = 60 a i r = 170 a typical i l and i r currents at v min limited by l & r pin duty limit pi-5885-082610
rev. c 02/11 10 tfs757-764hg www.powerint.com a resistor r fb is connected from the bypass pin to the feedback pin. this resistor feeds current into the feedback pin (whos voltage is clamped to approximately 1 v during this detection period). the current into the feedback pin is determined by the value of the resistor, and thus the input current (and indirectly the resistor value), select an internal current limit according to the following table. main line undervoltage detection (uv) the line-sense pin resistor is connected to v in and generates a current signal proportional to v in . the line-sense pin voltage is held by the device at 2.35 v. the line-sense pin current signal is used to trigger under/overvoltage thresholds for both the standby and main converters. assuming a line-sense pin resistor of 4 m w , the standby will begin operating when the line-sense pin current exceeds the (i l(sb-uvon) ) threshold, nominally approximately 100 v. however the main is still held in the off-state, until the line-sense pin current exceeds the (i l(ma-uvon) ) threshold, nominally 315 v for 4 m w . there is hysteresis for both main and standby undervoltage-off thresholds, to allow suffcient margin to avoid accidental triggering, and to provide suffcient margin to meet hold-up time requirements. bear in mind that the main converter may start to loose regulation before it fnally shuts down. this is because the dynamic duty cycle limit may clamp the duty cycle below that required for regulation at lower input voltages. once the input voltage falls below the 215 v (i l(ma_uvoff) ) threshold, the main will shutdown but standby will continue to operate. the standby will turn off when the input voltage drops below approximately 40 v (i l(sb-uvon) ). figure 9. current limit selection. table 3. feedback pin main current limit selection. i fb (threshold) i limit r en(select) (1%) 0.0-5.1 m a l1 60% ma open k w 5.1-11.9 m a l2 80% ma 511.0 k w 11.9-23.8 m a l3 100% ma 232.0 k w uv(on) standby , i (l) = 25 a 4.7 v 1 v 5.7 v i (l) v (bp) v (fb) v (en) t select - current limit selection occurs here during device start-up and before power supply switching 2.7 v 2.2 v 6.0 v after standby acheives regulation pi-5975-102610 figure 8. duty cycle limit vs. ratio of r pin current over l pin current. 0.5 1.0 1.5 2.0 3.0 2.5 i r /i l duty cycle limit 0.7 0.6 0.5 0.4 pi-5977-061010 i l = 60 a i l = 90 a i l = 100 a i l = 115 a
rev. c 02/11 11 tfs757-764hg www.powerint.com main reset overvoltage detection there is also an overvoltage threshold for the reset pin. when triggered, the reset overvoltage will shutdown only the main, leaving the standby in operation. standby power general introduction the standby is a wide range power supply, typically a fyback converter, operating over a wide input range (85-265 vac) and delivering up to 20 w continuous output power. the standby power supply provides two functions in most high-power applications. it provides a direct secondary output but also provide bias power to other primary-side devices (in particular typically a pfc boost converter). the hipertfs standby retains most features of the tinyswitch-iii, such as auto-restart, thermal shutdown, multi-level current limit on/off control, etc. the hipertfs standby controller has a few differences versus tinyswitch-iii: 1. there are 4 current limits that are selected via the enable pin (rather than by using different bypass pin capacitors as in tinyswitch-iii). there are 4 user selectable current limits 500, 550, 650, 750 ma design for secondary standby output power of 10, 12.5, 15 and 20 w. 2. secondary ovp latching shutdown. this is triggered via a current in excess of the bypass pin latching shutdown threshold (i bp(sd) = 15 ma). 3. dedicated line-sense pin for line-voltage detection providing absolute uv and ov on/off thresholds (unlike tinyswitch-iii which detects input voltage only during restart). 4. current limit is compensated as a function of input voltage to maintain a fat overload characteristic versus input voltage. in a high-power system, the standby power supply is the frst power supply to begin operating. the main converter cannot begin working until the standby is in operation. likewise the main converter will shutdown at a higher-voltage than the standby and thus the standby is always the last power supply to shutdown. standby on-chip current limit with external selection during start-up, the feedback pin and enable pin are both used to select internal current limits for the main and standby converters respectively. the detection period occurs at the initial start-up of the device (just after bypass pin voltage of 4.7 v is achieved), and before the main or standby mosfets start switching. this is done to minimize noise interference. the enable pin works in a similar way to the feedback pin selection. the only difference being that the enable pin is not clamped to 1 v during selection, instead remaining at 2.35 v during the detection period. thus the selection resistor values figure 10. main and standby start-up. i en (threshold) i limit r en (select) (1%) 0.0-8.5 m a l1 500 ma open k w 8.5-17.7 m a l2 650 ma 280.0 k w 17.7-33.0 m a l3 750 ma 137.0 k w 33.0-66.0 m a l4 550 ma 63.4 k w table 4. enable pin standby current limit selection. v in supply start-up sequence standby output main output v bp 12 ms 385 v 315 v 100 v 30 v 2-20 ms 6.0 v 4.7 v 5.7 v pi-5611a-062710 figure 11. l and r pin duty limit mode. v in standby output main output 385 v 300 v 240 v 40 v pi-5612a-060910 t holdup 20 ms typically turned off by secondary supervisor circuit, once regulation below limit t 1 t 2 t 3 t 4 r l r r to v in to clamp reset circuit r hipertfs l
rev. c 02/11 12 tfs757-764hg www.powerint.com are slightly different for the enable pin versus the feedback pin. the enable pin internal current selection is chosen according to the above table. the current limit selection for both feedback pin and enable pin takes place when the bypass pin frst reaches 4.7 v. once the short detection period is complete, the bypass pin is ramped on up to 5.7 v, and the feedback pin is allowed to foat to its nominal voltage of 3.5 v. standby line compensated current limit to flatten output overload for many power supplies, the power output capability of the power supply increases dramatically as the input voltage increases. this means that most power supplies are able to deliver much more power (up to 30-40% more power), into a fault overload when operating at higher input voltage (versus operating at lower input voltage). this can cause a problem since many specifcations require that the output overload power capability of the device is more tightly managed. in the case of the hipertfs, the standby current limit is adjusted as a function of line (input voltage), in such a ways as to always provide substantially the same maximum overload power capability. the input voltage is detected via the line-sense pin current and the internal standby current limit of the device is adjusted accordingly on a cycle-by-cycle basis. this means that the hipertfs standby will only deliver approximately 5% more overload power at high-line as it did at low-line. this feature provides a much safer design. standby line undervoltage detection (uv) the line-sense pin resistor is connected to v in and generates a current signal proportional to v in . the line-sense pin voltage is held by the device at 2.35 v. the line-sense pin current signal is used to trigger under/overvoltage thresholds for both the standby and main converters. assuming a line-sense pin resistor of 4 m w , the standby will begin operating at approximately 100 v (as defned by i l(sb_uvon) ). the standby will shutdown if regulation is lost when input voltage is below 100 v. however the standby will be forced to shutdown if this input voltage drops below approximately 40 v (as defned by i l(sb-uvoff) ). main and standby oscillator and switching frequency the standby converter operates at a frequency of 132 khz. the main converter operates at exactly half that frequency at 66 khz. the two converters both include a common frequency jitter profle that varies the switching frequency 4 khz for the main (twice the jitter frequency range 8 khz for the standby), during a 4 ms jitter period. the frequency jitter helps reduce quasi- peak and average emi emissions. it should be noted that the hipertfs has a collision avoidance scheme in which the main converter is the master and the standby is the slave, which avoids the main and standby switching at exactly simultaneous moments. the most common condition would be close to 50% duty cycle, if the main (master) is about to switch (turn-off), then the standby (slave), waits for short instant (200 ns) before starting its next cycle. the standby is used as the slave, since the on/off control of the hipertfs standby is less easily disrupted by sudden delays in switching, versus the linear control loop of the main converter. standby and main thermal shutdown the hipertfs provides a thermal shutdown function, (otp) that protects the hipertfs. this hysteretic thermal shutdown allows the device to automatically recover from any thermal fault event. the thermal shutdown is triggered at a die-temperature of approximately 118 c and has a high hysteresis to ensure the average device temperature is within safe levels. in a well designed system the hipertfs thermal shutdown is not triggered during any normal operation and is only present as a safety feature to protect against abnormal or fault conditions. bypass (bp) pin operation the bypass (bp) pin is the supply pin for the entire hipertfs device. the bypass pin is internally connected to a high-voltage current source via the standby drain power mosfet. this high-voltage source will charge the bypass pin to 4.7 v during initial power up. once the bypass pin reaches 4.7 v, the bypass pin will check the main and standby current limit selection (feedback pin and enable pin resistors respectively). this selection takes a very short period, thereafter the bypass pin continues being charged until it reaches 5.7 v, at which point the standby power supply is ready to begin operation. like the tinyswitch-iii the high-voltage current source will continue to charge the bypass pin if it droops below 5.7 v. however in most typical applications, a resistor (typically 7.5 k w ) is connected from primary bias (12 v) to the bypass pin. this resistor provides the operating current to the bypass pin, preventing the need to draw power from the high-voltage current source. like the tinyswitch-iii, the bypass pin contains a shunt regulator, which will be enabled if the bypass pin voltage is externally driven above 5.7 v. the bypass pin shunt current is used for two functions: 1. first, for a 4 ma threshold (i bp(on) ) for main remote-on. when the bypass pin current exceeds this threshold, the main is enabled. figure 12. shows output overload power for both compensated and uncompensated standby current limits. 50 100 150 200 250 300 400 450 350 v in dc (v) output overload power (%) 150 140 130 120 100 110 90 80 pi-5884-052510 not compensated compensated
rev. c 02/11 13 tfs757-764hg www.powerint.com output power table product 2 two-switched forward 380 v flyback 100 v - 400 v continuous 1 (25 c) continuous 1 (50 c) peak (50 c) 50 c tfs757hg 193 w 163 w 228 w 20 w TFS758HG 236 w 200 w 278 w 20 w tfs759hg 280 w 235 w 309 w 20 w tfs760hg 305 w 258 w 358 w 20 w tfs761hg 326 w 276 w 383 w 20 w tfs762hg 360 w 304 w 407 w 20 w tfs763hg 388 w 327 w 455 w 20 w tfs764hg 414 w 344 w 530 w 20 w table 5. output power table. notes: 1. maximum practical continuous power in an open frame design with adequate heat sinking (assuming heat sink c-a of <4 c/w), measured at specifed ambient temperature (see key applications considerations for more information). 2. package: esip16/12. (note: direct attach to heat sink, does not require insulation sil pad) 2. second a 15 ma threshold (i bp(sd) )for standby secondary ovp latch-off. when the bypass pin current exceeds this threshold, the standby and main converters are latched-off. this latch can be reset by pulling the line-sense pin below the line undervoltage threshold (i l(sb-uvoff) ), or by discharging the bypass pin below 4.7 v. note: unlike the tinyswitch-iii the hipertfs bypass pin capacitor does not provide any programming capability. instead the recommended bypass pin capacitor should always be a 1 m f (ceramic) capacitor. main and standby line overvoltage detection (ov) the overvoltage threshold is included in the device, and can be used to disable the device during overvoltage (with the use of an additional external signal zener). the overvoltage threshold is set suffciently high to prevent accidental triggering during boost pfc overshoot conditions. when the overvoltage condition is triggered, it will simultaneously shutdown both the main and standby. the overvoltage feature is intended for use with external components (circuitry), to program the overvoltage threshold independently of the undervoltage thresholds (see the applications section for details). high-power esip package the hipertfs package is designed to minimize the physical size of the device, while maintaining a low thermal impedance and suffcient electrical spacing for the pins. the package has 12 functional pins with 4 pins removed for increased pin-to-pin spacing between high-voltage pins. the low-side two-switch forward and fyback mosfets have a thermal impedance of less than 1 c/w to the exposed pad on the back of the package. since this pad is referenced to the source pin (source), it is at electrical ground potential and thus can be connected to the heat sink without need for electrical insulation. the high-side mosfet is over-molded to achieve electrical isolation and thus also allows direct connection to the heat sink.
rev. c 02/11 14 tfs757-764hg www.powerint.com design, assemble and layout considerations power table the data sheet power table (table 1, page 1) represents the maximum advised continuous power based on the following conditions; 1. typical multi-output pc main with the following outputs +12 v, +5 v, +3.3 v, -12 v, and +5 v standby. 2. a boost regulated dc input for main 300 vdc to 385 vdc minimum nominal of 375 vdc. 3. hipertfs total effciency at least 85% at full load. 4. schottky high-effciency output diodes. 5. dc input for standby 130 vdc to 385 vdc. 6. suffcient heat sinking and fan cooling to keep device temperature below 100 c. 7. transformer designed with nominal duty factor of 45%. hipertfs selection selecting the optimum hipertfs depends upon the continuous output power, thermal management, (heat sinking, etc.), and maximum ambient operating temperature. oem applications are typically 50 c max ambient while clone pc supplies are usually specifed at 25 c ambient. higher effciency can be achieved with the larger devices. the maximum output power can be tailored for any given device by programming primary i limit(ma) . hold-up time the input capacitor is a critical component in designing for a guaranteed minimum hold-up time. proper design of the transformers nominal duty cycle and suffcient primary winding clamp voltage for rest of main transformer are also essential. pixls (pi expert design spreadsheet) can compute these values or refer to formula in an-51. bias support for high-side driver bias support for hipertfs high-side switch is sourced from a forward phased winding of the main transformer and should provide a minimum of 17 v at 300 vdc input (or minimum input voltage at which regulation can be maintained) to guarantee the 12 v bias required for the high-side driver is maintained. primary bias support the standby converter provides a minimum 17 v output that biases the bypass pin of hipertfs. it is also the source for remote on/off control and ovp. this output should be capable of delivering a minimum of 20 ma. the primary bias flter capacitor should be at 330 m f to hold up the bias during the start-up transient. start-up there is a duty factor soft-start function at start-up that slews from 30% duty factor to max duty factor in approximately 15 ms. the current limit during start-up is actually boosted by 115% for the frst 32 ms to provide the ability to drive heavy capacitive loads and meet less than 20 ms output rise time requirement. figure 14. full range emi scan (132 khz with jitter) with identical circuitry and conditions. figure 15. typical primary winding clamp-to-rail. -20 -10 0 -10 20 30 40 50 60 70 80 0.15 1 10 30 frequency (mhz) amplitude (dbv) pi-2576-010600 en55022b (qp) en55022b (av) en55022b (qp) en55022b (av) -20 -10 0 -10 20 30 40 50 60 70 80 0.15 1 10 30 frequency (mhz) amplitude (dbv) pi-5856-030810 hd hs d g s hipertfs vddh r dr1 150 v +v bus rtn dr2 l fb en bp dsb pi-5846-111810 control figure 13. fixed frequency operation without jitter.
rev. c 02/11 15 tfs757-764hg www.powerint.com emi the frequency jitter feature modulates the switching frequency over a narrow band as a means to reduce conducted emi average and quasi-peaks associated with the harmonics of the fundamental switching frequency. this is particularly benefcial for average conduction mode where the sampling bandwidth is narrow. the modulation rate is nominally 250 hz which is high enough to reduce emi but low enough to have negligible effect on output ripple (rejected by control loop). transformer design it is recommended that the transformer be designed for a maximum fux density of 3000 gauss during continuous maximum output power and a maximum peak transient fux density no greater than 4000 gauss. the turns ratio should be chosen for a nominal duty factor of 45% at 385 vdc input to guarantee transformer reset with typical primary winding clamp-to-rail (figure 15). for nominal duty factor of higher value it is recommend to refer to an-51 and use pixls spreadsheet for optimal transformer design. typically the transformer should have foil secondary windings for outputs above 10 amps. the primary winding should be split primary type to keep leakage inductance low. standby mode consumption the hipertfs standby converter is essentially a tinyswitch-iii controller which uses whole-cycle on/off control. this has the beneft of operating at a low average frequency at lighter loads which increases effciency and reducers no-load consumption. heat sinking the hipertfs package is esip-16/12. there is a metal exposed pad that provides a low thermal path to the heat sink for the low-side power device and standby power device. there is also figure 16. hipertfs layout considerations. figure 17. hipertfs heat sink mounting. hd hs d g s hipertfs vddh to bulk capacitor r l fb en bp dsb control pi-5883-032410 an over-molded, electrically isolated section of the package backside that provides isolation between the heat sink and the internal high-side switch. thermal heat sink compound, and a mounting clip providing a minimum torque of 50 newtons, are required for good thermal performance. the heat sink temperature behind device should not exceed 95 c to avoid activating the over-temperature shutdown of hipertfs. since some of the hipertfs pins are bent towards the heat sink, there needs to be a minimum of 0.078 inches clearance between heat sink and pc board. layout considerations use a single point connection between, source pin, ground pin and bypass capacitor. typically the bypass capacitor is a surface mount type and is located directly under the hipertfs package between the ground pin and the bypass pin. the feedback pin and enable pin along with the line- sense and reset pins should be kept away from noisy, high voltage switching areas. if it is unavoidable to have long traces connecting to feedback pins then route these traces close to quiet, low impedance traces, that act as a faraday shield. the line-sense and reset pins are associated with multiple series resistor sections due to the high-voltage sensing. make sure the last resistor in series chain is smd type and place it very close to the pin. this will minimize the pick-up of noise. the primary auxiliary bias output rectifer and flter should be star referenced to bulk capacitor. any y capacitors referenced to dc primary should also be tied to quiet nodes of bulk capacitor negative or positive terminal. pi-5882-111710 minimum clearance is 0.078 inches ~50 newtons
rev. c 02/11 16 tfs757-764hg www.powerint.com figure 18. high-side bias. figure 19. latching output ovp. hd hs d g s hipertfs vddh r l fb en bp dsb control pi-5881-082610 c 3 c 1 r 1 v in v aux c 2 c r1 minimum supply current to vddh = 1 ma main transformer v high_bias standby transformer v high_bias_(min) = v aux_(min) = 14 v v high_bias ?v ddh 1 ma r 1_max = hd hs d g s hipertfs vddh r l fb en bp dsb control pi-5879-111710 g s v bias v out r 1 ic 1 (ctr = 1) v 1 v out(ov) = (15 ma r 1 ) + v 1 + 1 i ovp 15 ma
rev. c 02/11 17 tfs757-764hg www.powerint.com figure 20. non-latching output ovp. figure 21. remote on and standby bias. hd hs d g s hipertfs vddh r l fb en bp dsb control pi-5878-111710 v out v 1 v out(ov) = v 1 + 1 v v in v bias r 1 r 1 v aux - v ce_opto i l(ma_ovoff) r 1 12 v - 0.3 v 146 a hd hs d g s hipertfs vddh r l fb en bp dsb control pi-5877-111710 standby out v bias r 3 10 k q1 r 4 1 k 13 v rem r 1 6 v r 2 i remote_min = 1 ma i standby_min = 900 a i on_min = 5 ma v on r 1 = v on - 6.7 v 5 ma r 2 = v aux(min) - 6 v 900 a remote on
rev. c 02/11 18 tfs757-764hg www.powerint.com figure 22. input ovp (latching). figure 23. non-latching input ovp. hd hs d g s hipertfs vddh r l fb en bp dsb control pi-5875-111710 v bias 20 k 100 k 10 k r 1 90 k vr1 (+12 v) v in r 2 3.9 m r 1 + r 2 = 4 m i l(ov) = v in(ov) r 1 + r 2 r 1 = vr1 - 1.9 v i l(ov) hd hs d g s hipertfs vddh r l fb en bp dsb control pi-5876-111710 v in v bias r 1 90 k vr1 (+12 v) 300 k 10 k r 2 3.9 m r 1 + r 2 = 4 m i l(ov) = v in(ov) r 1 + r 2 r 1 = vr1 - 1.9 v i l(ov) 100 k q1
rev. c 02/11 19 tfs757-764hg www.powerint.com figure 24. fast ac reset of bp latch. figure 25. l and r pin reset and duty limit circuit. hd hs d g s hipertfs vddh r l fb en bp dsb control pi-5873-020411 r 1 r 2 150 v r 1 = r 2 = 4 m hd hs ac input d g s hipertfs vddh l n r l fb en bp dsb control pi-5874-111710 100 k q1 q2 0.1 f 1 m 6.8 m v bias 6.8 m 1 m
rev. c 02/11 20 tfs757-764hg www.powerint.com figure 26. l and r pin duty limit with r l = 4 m w and r r = 4 m w . applications example high effciency +12 v, 25 a main output and +5 v 2.5 a standby power supply the circuit in figure 26 is an example of a design using hipertfs providing a 300 w +12 v output forward derived main converter and a 12 w +5 v standby output from the fyback controller of hipertfs. the very high integration of two full converters within a single package immediately shows the result of very low external parts count for the entire design. both the main converter and the fyback section of hipertfs are designed to give very high-effciency. the main converter takes advantage of the ability to operate above 50% duty factor which lowers rms switch currents and allows using lower voltage more effcient schottky diodes on the output. the fyback section uses power integrations tinyswitch technology which is often used in designs that demand high-effciency and low no-load input power consumption. the design in figure 27 is intended to work with a pfc boost front end that nominally provides a 385 vdc input. the main converter will regulate to full load between 300 vdc and 385 vdc. this voltage range guarantees greater than 20 ms hold-up time with c1 (270 m f). the standby section is designed to operate whether the boost pfc stage is on or off. the standby therefore is designed to operate from 100 vdc to 385 vdc which covers the normal universal input of 90 vac to 265 vac. the start-up sequence is initiated with hipertfs charging the bypass pin capacitor via internal high-voltage current source. current limit selection then follows via feedback pin and enable pin resistors. the hipertfs then senses the input voltage via the line-sense pin resistor series chain r12, r13, r35. when the input voltage reaches 100 v vdc the line- sense pin uv standby threshold is reached and the standby converter turns on. after several milliseconds the standby output will reach regulation and the primary v on +12 v bias will be stable. when the input bulk voltage reaches 315 vdc which is the uv threshold for the main converter, the main converter will initiate a turn on sequence once the remote-on command from secondary is activated. the remote-on switch (sw1) on the secondary-side for this particular design allows the user to manually activate that main converter by turning on the remote-on optocoupler. in actual pc designs the remote- on would be controlled by a computer start-up command. this optocoupler sources 5 ma into the bypass pin of the hipertfs which is the threshold current to start the turn on sequence for pi-5880-111710 regulation (fb) duty cycle reset duty clamp hard limit to v in to clamp reset circuit available duty cycle range duty factor 60% r l r r 45% 100 a (385 v) 75 a (300 v) l pin current (v in with r l = 4 m) l and r pin transformer reset and forward duty clamp protection r l hipertfs forward duty clamp this region for transient response
rev. c 02/11 21 tfs757-764hg www.powerint.com figure 27. schematic of high-effciency +12 v, 25 a main output and +5 v, 2.5 a standby power supply. the main converter. the main converter will f rst turn on the bottom switch to allow the high-side drive to receive the boot- strap bias. after 14 ms the main converter will start switching both switches at 66 khz and the main output voltage will rise. once the regulator u5 becomes active, current will fow through the optocoupler u1. the collector of u1 will sink current out of the feedback pin to adjust for appropriate duty cycle to maintain regulation. the normal operating sink current is between 1 ma and 2 ma. there is a forward phased bias winding off the main transformer that provides sustained bias for the high-side driver. during normal and brownout operation the reset pin senses the turn off clamp voltage via the resistor chain r6, r18, r19 and the internal controller determines the maximum safe duty factor by comparing the reset pin current with the line-sense pin current. this features guarantees that saturation of the transformer is completely avoided in all conditions including brownout and load transients. the line- sense pin also has a uv low threshold which turns off the main converter when the input voltage is below 215 v. this design in particular is intended to operate with a minimum of 30 cfm airfow at full load. both the main and standby output have overvoltage protection from sense circuit around u4 which will source >15 ma during fault into bypass pin to cause latching shut-off of both converters. the standby uses auto-restart to protect the standby output from overpower and over-current. the main output is current limited by the selected internal primary current limit of the main switch path. hd 14 - 25 v d5 bav20 vr4 mmsz5243bt1g 13 v d7 m6060c-e3/45 d6 m6060c-e3/45 d9 uf4005 c21 2.2 nf l1 3.3 h c4 100 nf c5 47 nf c10 3300 f c11 3300 f r21 2 k r28 100 r30 1 k r34 4.75 k r31 4.75 k u7 lm431 u5 lm431 r33 1 k r32 4.7 k sw1 remote on/off u3a pc817xi1j00f r24 3.92 k r3 100 r4 150 rtn 5 v 12 v d2 u4a pc817xi1jd0f vr1 zmm5242b-7 12 v vr2 zmm5230b-7 4.7 v r15 750 u1a pc817xi1j00f r9 15 k r10 221 c9 1 nf d8 uf4005 c19 1 nf c20 330 f *optional component for accidental reverse connection r26 47 c17 2200 f u2a pc817xi1j00f c14 470 nf c16 330 nf c15 2200 f c13 100 nf u2b pc817xi1j00f u1b pc817xi1j00f r25 232 k r27 280 k d10 bas16ht1g j3-1 j4-1 j3-3 r14 2 k c6 100 nf c3 100 nf d3 1n4007 r5 4.7 r1 2.2 c1 270 f f2 4 a d13* 1n5404 r20 4.7 k r16 7.5 k r17 820 r35 1.33 m r13 1.33 m r12 1.33 m r23 1 k r22 4.7 k u3b pc817x1j00f u4b pc817x1j00f r6 100 vr3 p6ke150a r18 1.33 m r19 1.33 m r36 1.33 m r8 4.7 u6 tfs762hg d4 1n4007 d12 rgp100 d11 stps1045b 3 5 2 1 2 6 9,10 9,10 13,14 1 hs 380 vdc rtn rtn fb en t standby t main d g s 5 6 vddh 13 r l fb bp en 7 9 10 11 8 dsb 16 14 1 3 pi-5969-102810 c12 1 f 6,7 control +12 v +5 v r29 470 l2 2.2 h r7 4.7 c18 1 nf c2 3.3 nf c8 100 nf r11 43.2 k q1 mmbt4401
rev. c 02/11 22 tfs757-764hg www.powerint.com figure 28. layout of high-effciency +12 v, 25 a main output and +5 v, 2.5 a standby power supply. + C hv pi-5872-042710 transformer l1 d1 d7 vr1 vr2 d6 c10+ d2 sw1 r4 l2 r26 r29 vr4 r17 r22 c18 c20 j4 c7 c17 t2 u4 u2 u7 u3 r32 r33 c13 c8 c9 r11 c2 r10 c4 r24 r21 r15 d8 r12 r1 c2 d5 r14 r15 c12 r27 r34 r20 r16 d12 d10 r23 c16 r3 r31 r28 c14 r30 c15 c21 f1 j3 + c1 c16 c3 c13 vr3 d3 tp1 r6 c11+ j1 r9 j2 r13 r18 r36 d4 r7 r8 r35 d9 c6 r25 y capacitor hf lc post-filter 5 v + C 12 v + C
rev. c 02/11 23 tfs757-764hg www.powerint.com parameter symbol conditions source = 0 v; t j = 0 c to 100 c (unless otherwise specifed) min typ max units control functions switching frequency - pc main f s(ma) t j = 25 c average 62 66 70 khz peak-to-peak jitter 4 frequency jitter modulation rate f m(ma) 250 hz remote-on main bypass pin remote-on current i bp(on) v en = open 3.2 3.8 4.4 ma bypass pin remote- off current hysteresis i bp(off) 1.1 ma bypass pin latching shutdown threshold i bp(sd) 13 15.5 17.5 ma main/standby remote- on delay t r(on) 2.5 m s main/standby remote- off delay t r(off) 2.5 m s main/standby remote- off long time period t r(period) 80 m s absolute maximum ratings (1,5) drain voltage high-side mosfet .......................-0.3 v to 530 v drain peak current high-side: tfs757 ................... 3.1 (5.9 ) 4 a tfs758 ................... 4.5 (8.4) 4 a tfs759 ................... 5.0 (9.3) 4 a tfs760 ................. 5.7 (10.7) 4 a tfs761 .................. 6 .1 (11.4) 4 a tfs762 .................. 6 .4 (12.1) 4 a tfs763 ................. 7. 2 (13 . 4) 4 a tfs764 ................. 8.3 (15.5) 4 a drain voltage low-side mosfet .................... -0.3 v to 725 v drain peak current low-side: tfs757 ................... 3.1 (5.9 ) 4 a tfs758 ................... 4.5 (8.4) 4 a tfs759 ................... 5.0 (9.3) 4 a tfs760 ................. 5.7 (10.7) 4 a tfs761 .................. 6 .1 (11.4) 4 a tfs762 .................. 6 .4 (12.1) 4 a tfs763 ................. 7. 2 (13 . 4) 4 a tfs764 ................. 8.3 (15.5) 4 a drain voltage standby mosfet ...................... -0.3 v to 725 v drain peak current standby mosfet ................ 1.20 (2.25) 4 a enable (en) pin voltage ..................... ....................... -0.3 v to 9 v enable (en) pin current ................. ................................. 100 ma feedback (fb) pin voltage ................. ...................... -0.3 v to 9 v feedback (fb) current ................... ................................. 100 ma line sense (l) pin voltage ............................................-0.3 v to 9 v line sense (l) pin current ............................................ ....... 100 ma reset (r) pin voltage ..................... ........................... -0.3 v to 9 v reset (r) pin current ..................................... .................... 100 ma bypass supply (bp) pin voltage ................... ............ -0.3 v to 9 v bypass supply (bp) pin current ................................... ..... 100 ma high side (vddh) supply pin voltage ................. -0.3 v to 13.4 v high side (vddh) supply pin current ..................................50 ma storage temperature ............................................ -65 c to 150 c operating junction temperature (2) .......................-40 c to 150 c lead temperature (3) ................................................................. 260 c notes: 1. all voltages referenced to source, t j = 25 c. 2. normally limited by internal circuitry. 3. 1/16 in. (1.59 mm) from case for 5 seconds. 4. the higher peak drain current is allowed while the drain voltage is simultaneously less than 400 v. 5. maximum ratings specifed may be applied one at a time, without causing permanent damage to the product. exposure to absolute rating conditions for extended periods of time may affect product reliability. thermal resistance high-side mosfet ( jc ) tfs757, tfs758 .................... 15 c/w tfs759, tfs760 .................... 14 c/w tfs761, tfs762 .................... 13 c/w tfs763, tfs764 .................... 12 c/w low-side mosfet ( jc ) ................................................ 1 c/w notes: 1. all voltages referenced to source, t a = 25 c. soft-start high-side start-up charge time t d(ch) 14 ms main current limit at start-up i lim(ss) see note a 115 % soft-start period 12 ms
rev. c 02/11 24 tfs757-764hg www.powerint.com parameter symbol conditions source = 0 v; t j = 0 c to 100 c (unless otherwise specifed) min typ max units feedback pin pwm gain dc reg(ma) -1800 m a < i fb < -1500 m a, i l = 60 m a, i r = 160 m a -70 %/ma pwm gain temperature drift tc dcreg 0.05 %/c feedback pin feed- back onset current i fb(on) i l = 60 m a, i r = 170 m a t j = 25 c -1.1 ma feedback pin current at zero duty cycle i fb(off) -2.1 ma feedback pin internal filter pole p fb 12 khz feedback pin voltage v fb i fb (off) , i fb = i fb(on) 3.56 v line-sense pin (line voltage) line undervoltage threshold C standby i l(sb-uvon) t j = 25 c threshold 25 m a i l(sb-uvoff) 10 line undervoltage threshold C main i l(ma-uvon) t j = 25 c threshold 76 80 84 m a i l(ma-uvoff) threshold 47 53 58 line overvoltage threshold C main and standby i l(ma-ovon) t j = 25 c threshold 119 135 146 m a i l(ma-ovoff) threshold 135 146 164 line-sense pin voltage v l i l = 79 m a 2.4 v i l = 149 m a 2.5 line-sense pin short circuit i l(sc) v l = v bp 375 m a reset pin (duty limit/main only remote-off) reset overvoltage threshold i r(ma-ovon) t j = 25 c threshold 165 205 245 m a i r(ma-ovoff) threshold 175 215 255 reset pin voltage v r i r = 155 m a 2.5 v reset pin short circuit current i r(sc) v r = v bp 375 m a duty cycle C programmable limit dc limit(ma) i l = 100 m a , i r = 110 m a 50.5 % i l = 115 m a , i r = 140 m a 47.5 dc max(ma) i l = 100 m a , i r = 170 m a 63 current limit programming feedback pin current limit detection range #1 i lim(1)(ma) start-up see note c 0-5 m a feedback pin current limit detection range #2 i lim(2)(ma) start-up see note c 5-12 m a feedback pin current limit detection range #3 i lim(3)(ma) start-up see note c 12-24 m a
rev. c 02/11 25 tfs757-764hg www.powerint.com parameter symbol conditions source = 0 v; t j = 0 c to 100 c (unless otherwise specifed) min typ max units maximum current limit current limit i lim(1)(ma) tfs757 t j = 25 c di/dt = 175 ma/ m s 1.02 a i lim(2)(ma) di/dt = 233 ma/ m s 1.36 i lim(3)(ma) di/dt = 291 ma/ m s 1.58 1.70 1.82 i lim(1)(ma) tfs758 t j = 25 c di/dt = 250 ma/ m s 1.45 i lim(2)(ma) di/dt = 335 ma/ m s 1.95 i lim(3)(ma) di/dt = 420 ma/ m s 2.28 2.45 2.62 i lim(1)(ma) tfs759 t j = 25 c di/dt = 258 ma/ m s 1.62 i lim(2)(ma) di/dt = 344 ma/ m s 2.16 i lim(3)(ma) di/dt = 430 ma/ m s 2.55 2.70 2.94 i lim(1)(ma) tfs760 t j = 25 c di/dt = 324 ma/ m s 1.86 i lim(2)(ma) di/dt = 432 ma/ m s 2.48 i lim(3)(ma) di/dt = 540 ma/ m s 2.88 3.10 3.30 i lim(1)(ma) tfs761 t j = 25 c di/dt = 338 ma/ m s 1.95 i lim(2)(ma) di/dt = 450 ma/ m s 2.65 i lim(3)(ma) di/dt = 564 ma/ m s 3.07 3.30 3.53 i lim(1)(ma) tfs762 t j = 25 c di/dt = 360 ma/ m s 2.10 i lim(2)(ma) di/dt = 480 ma/ m s 2.80 i lim(3)(ma) di/dt = 600 ma/ m s 3.25 3.50 3.75 i lim(1)(ma) tfs763 t j = 25 c di/dt = 402 ma/ m s 2.35 i lim(2)(ma) di/dt = 402 ma/ m s 3.10 i lim(3)(ma) di/dt = 670 ma/ m s 3.60 3.90 4.16 i lim(1)(ma) tfs764 t j = 25 c di/dt = 468 ma/ m s 2.70 i lim(2)(ma) di/dt = 624 ma/ m s 3.60 i lim(3)(ma) di/dt = 780 ma/ m s 4.18 4.50 4.81 low-side main mosfet on-state resistance r ds(on) tfs757 i d = i lim(3)(ma) t j = 25 c 4.87 5.60 w t j = 100 c 7.69 9.05 tfs758 i d = i lim(3)(ma) t j = 25 c 3.25 3.73 t j = 100 c 4.90 5.83 tfs759 i d = i lim(3)(ma) t j = 25 c 2.35 2.70 t j = 100 c 3.60 4.21 tfs760 i d = i lim(3)(ma) t j = 25 c 1.96 2.24 t j = 100 c 2.80 3.29 tfs761 i d = i lim(3)(ma) t j = 25 c 1.60 1.85 t j = 100 c 2.30 2.75 tfs762 i d = i lim(3)(ma) t j = 25 c 1.40 1.60 t j = 100 c 2.00 2.35 tfs763 i d = i lim(3)(ma) t j = 25 c 1.20 1.40 t j = 100 c 1.70 2.05 tfs764 i d = i lim(3)(ma) t j = 25 c 1.10 1.26 t j = 100 c 1.53 1.80 off-state drain leakage current i dss(d) tfs757 v l , v r = 0 v, i bp = 6 ma, v ds = 560 v, t j = 100 c 150 m a tfs758 150 tfs759 150 tfs760 150 tfs761 470 tfs762 470
rev. c 02/11 26 tfs757-764hg www.powerint.com parameter symbol conditions source = 0 v; t j = 0 c to 100 c (unless otherwise specifed) min typ max units low-side main mosfet (cont.) off-state drain leakage current i dss(d) tfs763 v l , v r = 0 v, i bp = 6 ma, v ds = 560 v, t j = 100 c 470 m a tfs764 470 breakdown voltage bv dss(d) v l , v r = 0 v, i bp = 6 ma, t j = 25 c 725 v rise time t r(d) 100 ns fall time t f(d) 50 ns high-side main mosfet on-state resistance r ds(on)(hd) tfs757 i d = i lim(3)(ma) t j = 25 c 1.76 w t j = 100 c 2.12 tfs758 i d = i lim(3)(ma) t j = 25 c 1.15 t j = 100 c 1.40 tfs759 i d = i lim(3)(ma) t j = 25 c 0.88 t j = 100 c 1.06 tfs760 i d = i lim(3)(ma) t j = 25 c 0.88 t j = 100 c 1.06 tfs761 i d = i lim(3)(ma) t j = 25 c 0.69 t j = 100 c 0.84 tfs762 i d = i lim(3)(ma) t j = 25 c 0.58 t j = 100 c 0.7 tfs763 i d = i lim(3)(ma ) t j = 25 c 0.46 t j = 100 c 0.56 tfs764 i d = i lim(3)(ma) t j = 25 c 0.46 t j = 100 c 0.56 effective output capacitance c oss(eff)(hd) tfs757 t j = 25 c, v gs = 0 v v ds = 0 v to 80% v dss(hd) 55 pf tfs758 82 tfs759 110 tfs760 110 tfs761 140 tfs762 165 tfs763 205 tfs764 205 breakdown voltage bv dss(hd) t j = 25 c 530 v off-state drain current leakage i dss(hd) tfs757 v d = 424 v, t j = 100 c 60 m a tfs758 60 tfs759 60 tfs760 60 tfs761 65 tfs762 80 tfs763 110 tfs764 110 turn-on voltage rise time t r(hd) 30 ns turn-off voltage fall time t f(hd) 25 ns
rev. c 02/11 27 tfs757-764hg www.powerint.com parameter symbol conditions source = 0 v; t j = 0 c to 100 c (unless otherwise specifed) min typ max units high-side main mosfet (cont.) high-side bias shunt voltage v ddh(shunt) see note b i ddh = 2 ma 11.4 12.1 12.8 v high-side undervoltage on-threshold v ddh(uvon) see note b 10.7 11.1 11.5 v high-side undervoltage off-threshold v ddh(uvoff) see note b 9.5 9.9 10.3 v high-side shunt hysteresis voltage v ddh(hyst) see note b 0.7 1.2 1.5 v standby mosfet on-state resistance r ds(on)(ds) i dsb = i lim(3)(dsb) t j = 25 c 3.7 4.37 w t j = 100 c 5.5 6.25 off-state drain leakage current i dss1(ds) v bp = 6.2 v v en = 0 v v ds = 560 v t j = 100 c 200 m a i dss2(ds) v bp = 6.2 v v en = 0 v v ds = 375 v, t j = 50 c 15 breakdown voltage bv dss(ds) v bp = 6.2 v, v en = 0 v, t j = 25 c 725 v drain supply voltage v dsb(start) 50 v standby controller output frequency in standard mode f s(sb) t j = 25 c average 124 132 140 khz peak-to-peak jitter 8 maximum duty cycle dc max(dsb) i l = 40 m a 67 70 73 % enable pin upper turnoff threshold current i dis -150 -115 -80 m a enable pin voltage v en i en = 25 m a 2.0 2.4 2.8 v i en = -25 m a 0.8 1.2 1.6 bypass pin charge current i ch1 v bp = 0 v, t j = 25 c -5 -3.2 -2 ma i ch2 v bp = 4 v, t j = 25 c -4 -1.5 0 bypass pin voltage v bp v ds = 50 v 5.50 5.70 5.90 v bypass pin voltage hysteresis v bp(hyst) 0.80 1.0 1.20 v bypass pin shunt voltage v bp(shunt) i bp = 2 ma 5.8 6.0 6.2 v standby circuit protection enable pin current limit selection range #1 i lim(1)(dsb) start-up 0-8.5 m a
rev. c 02/11 28 tfs757-764hg www.powerint.com parameter symbol conditions source = 0 v; t j = 0 c to 100 c (unless otherwise specifed) min typ max units standby circuit protection (cont.) enable pin current limit selection range #2 i lim(2)(dsb) start-up 8.5-18 m a enable pin current limit selection range #3 i lim(3)(dsb) start-up 18-33 m a enable pin current limit selection range #4 i lim(4)(dsb) start-up 33-60 m a standby current limit i lim(1)(dsb) i l = 20 m a , di/dt = 95 ma / m s , t j = 25 c 450 500 550 ma i lim(2)(dsb) i l = 20 m a , di/dt = 125 ma / m s , t j = 25 c 600 650 700 i lim(3)(dsb) i l = 20 m a , di/dt = 143 ma / m s , t j = 25 c 675 750 825 i lim(4)(dsb) i l = 20 m a , di/dt = 105 ma / m s , t j = 25 c 495 550 605 i lim i lim (i l = 100 m a) / i lim (i l = 20 m a) di/dt = 125 ma/ m s 80 % general circuit protection power coeffcient i 2 f i 2 f = i lim(2)(dsb)(typ) f s(sb)(osc)(typ) t j = 25 c 0.9 i 2 f i 2 f 1.12 i 2 f a 2 hz initial current limit i init t j = 25 c 0.75 i lim(min) leading edge blanking time (main) t leb(d) t j = 25 c 170 215 ns leading edge blanking time (standby) t leb(dsb) t j = 25 c 170 215 ns current limit delay (main) t ild(d) t j = 25 c 150 ns current limit delay (standby) t ild(dsb) t j = 25 c 150 ns thermal shutdown temperature t sd 118 c thermal shutdown hysteresis t sd(hyst) 55 c auto-restart on-time at f osc standby t ar t j = 25 c 64 ms auto-restart duty cycle standby dc ar t j = 25 c 2.2 % supply current drain supply current i s1 en current > i dis (no mosfets switching) 400 750 1000 m a i s2 en open (standby mosfet switching at f osc ) 600 950 1200 notes: a. the current limit is boosted for the frst 34 ms of main supply switching and returns to normal level after this period . b. v ddh(shunt) minus v ddh(uv_on) is equal to 250 mv minimum. c. level 1 r fb = open, level 2 r fb = 511 k w , level 3 r fb = 232 k w . d. level 1 r en = open, level 2 r en = 280 k w , level 3 r en = 137 k w , level 4 r en = 63.4 k w .
rev. c 02/11 29 tfs757-764hg www.powerint.com 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-6003-060210 standby drain pin current limit (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-6002-060210 main drain pin current limit (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 junction temperature ( c) pi-6001-060210 standby drain pin output frequency (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-6000-060210 main drain pin output frequency (normalized to 25 c) 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) standby drain pin breakdown voltage (normalized to 25 c) pi-5999-060210 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) main drain pin breakdown voltage (normalized to 25 c) pi-5998-060210 typical performance characteristics figure 29. main supply. breakdown voltage vs. temperature. figure 30. standby supply. breakdown vs. temperature. figure 31. main supply. frequency vs. temperature. figure 32. standby supply. frequency vs. temperature. figure 33. main supply. internal current limit vs. temperature. figure 34. standby supply. external current limit vs. temperature with r il = 10.5 k w
rev. c 02/11 30 tfs757-764hg www.powerint.com 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 junction temperature ( c) pi-5959-060210 standby drain pin undervoltage threshold (normalized to 25 c) typical performance characteristics (cont.) figure 36. l pin voltage vs. l pin current. figure 37. r pin voltage vs. r pin current. figure 38. feedback pin current vs. feedback pin voltage. figure 39. enable pin current vs. enable pin voltage. figure 40. bypass pin current vs. bypass pin voltage. figure 35. standby supply. undervoltage threshold vs. junction temperature. 0 0 20 40 80 100 120 140 60 160 l pin current ( a) l pin voltage (v) pi-5955-051210 4 2 3 1 5 0 0 50 150 200 100 250 r pin current (a) r pin voltage (v) pi-5954-050510 4 2 3 1 5 -5 feedback pin voltage (v) feedback pin current (ma) pi-5953-051210 0 -1 -2 -3 -4 1 0 1 2 3 4 5 7 6 -200 enable pin voltage (v) enable pin current (a) pi-5952-051210 300 200 100 0 -100 500 400 0 1 2 3 4 5 7 6 0 0.0 2.0 4.0 6.0 8.0 bypass pin voltage (v) bypass pin current (ma) pi-5951-050510 20 10 30
rev. c 02/11 31 tfs757-764hg www.powerint.com typical performance characteristics (cont.) 0 0 4 8 12 16 vddh votage (v) vddh current (ma) pi-5950-012711 20 10 30 0 -50 -25 0 25 50 75 100 125 temperature (c) duty cycle (%) pi-5949-052510 50 75 25 100 0 -50 -25 0 25 50 75 100 125 temperature (c) duty cycle (%) pi-5948-052510 50 75 25 100 0 0 2 4 6 8 10 12 14 16 18 20 standby drain voltage (v) drain current (a) pi-5942-060110 1 1.5 .5 t case = 25 c t case = 100 c 2 2.5 5 0 0 2 4 6 8 10 12 14 16 18 20 drain voltage (v) drain current (a) pi-5943-091010 2 1 t case = 25 c t case = 100 c 4 3 tfs757 0.4 tfs758 0.6 tfs759 0.8 tfs760 1.0 tfs761 1.2 tfs762 1.4 tfs763 1.6 tfs764 1.8 scaling factors: 0 100 200 300 400 500 600 0 10 100 1000 pi-5944-060110 standby drain pin voltage (v) drain capacitance (pf) figure 41. vddh current vs. vddh voltage. figure 43. duty cycle vs. temperature (i l = 115 m a, i r = 140 m a) figure 45. drain supply. output characteristics. figure 42. duty cycle vs. temperature (t j = 100 m a, j r = 110 m a). figure 44. standby supply. output characteristics. figure 46. standby supply. drain capacitance vs. drain voltage.
rev. c 02/11 32 tfs757-764hg www.powerint.com typical performance characteristics (cont.) 0 100 200 300 400 500 600 10 100 1000 10000 pi-5945-091010 drain pin voltage (v) drain capacitance (pf) tfs757 0.4 tfs758 0.6 tfs759 0.8 tfs760 1.0 tfs761 1.2 tfs762 1.4 tfs763 1.6 tfs764 1.8 scaling factors: 250 200 100 100 150 0 0 200 100 400 500 600 300 700 standby drain pin voltage (v) power (mw) pi-5946-060110 132 khz 500 400 200 100 300 0 0 200 100 400 500 600 300 700 power (mw) pi-5947-091010 66 khz drain pin voltage (v) tfs757 0.4 tfs758 0.6 tfs759 0.8 tfs760 1.0 tfs761 1.2 tfs762 1.4 tfs763 1.6 tfs764 1.8 scaling factors: figure 47. main supply. drain capacitance vs. drain voltage. figure 48. standby supply. power vs. drain voltage. figure 49. main supply. power vs. drain voltage. figure 50. high-side mosfet drain current vs. drain voltage. figure 51. high-side mosfet drain current vs. drain voltage. figure 52. high-side mosfet breakdown voltage vs. temperature. 20 0 0 1 2 3 4 5 6 7 drain voltage (v) drain current (a) pi-5970-091010 5 15 10 25 c 100 c t j = 25 c t j = 100 c tfs757 0.17 tfs758 0.25 tfs759/760 0.33 tfs761 0.42 tfs762 0.50 tfs763/764 0.63 scaling factors: 0 100 200 300 400 100 1000 pi-5971-083110 drain voltage (vhd-vhs) c oss (pf) tfs757 0.17 tfs758 0.25 tfs759/760 0.33 tfs761 0.42 tfs762 0.50 tfs763/764 0.63 scaling factors: 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 temperature ( c) breakdown voltage (normalized to 25 c) pi-5972-051210
rev. c 02/11 33 tfs757-764hg www.powerint.com typical performance characteristics (cont.) 2 1.5 1 0.5 0 0 100 200 300 400 drain voltage (vd) power (mw) pi-5973-083110 tfs757 0.17 tfs758 0.25 tfs759/760 0.33 tfs761 0.42 tfs762 0.50 tfs763/764 0.63 scaling factors: 66 khz figure 53. high-side mosfet power vs. drain voltage.
rev. c 02/11 34 tfs757-764hg www.powerint.com pin 1 0.235 (5.96) ref. 0.010 (0.25) typ. 0.041 (1.04) ref. 0.167 (4.24) ref. 0.101 (2.57) ref. 0.012 (0.30) typ. 0.020 (0.51) ref. 0.035 (0.89) ref. top-end view b-b location of exposed metal tie-bars pi-5300-021411 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremesof the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and inter- lead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 (0.18) per side . 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. pin #6 is the only straight (unformed) lead. 6. controlling dimensions in inches (mm). 7 8. tied to source (pin 6). 9. tied to hs (pin 14). 10 11. tied to hd (pin 16). esip-16b (h package) 0.381 (9.68) ref. 0.519 (13.18) ref. 0.012 (0.30) ref. 0.628 (15.95) ref. 0.019 (0.48) ref. 0.027 (0.70) 0.023 (0.58) 0.020 (0.50) 0.060 (1.52) ref. 10 ref. all around 0.016 (0.41) ref. 0.290 (7.37) ref. detail a 0.076 (1.93) 0.118 (3.00) 0.038 (0.97) 0.056 (1.42) ref. 16 13 14 11 10 9 9 8 7 5 6 3 1 pin 1 i.d. 0.118 (3.00) 0.201 (5.11) ref. front view side view back view detail a (n.t.s) bottom-end view 0.207 (5.26) 0.187 (4.75) 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 12 0.024 (0.61) 0.019 (0.48) 0.010 m 0.25 m c a b 4 3 12 0.016 (0.41) 0.011 (0.28) 0.020 m 0.51 m c 3 0.653 (16.59) 0.647 (16.43) 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) 2 0.325 (8.25) 0.320 (8.13) 2 5 5 5 c a b b b mounting hole pattern (n.t.s) all dimensions in inches (mm) 0.152 (3.88) 5 1 0.164 (4.18) 6 0.114 (2.91) 7 9 11 14 0.114 (2.91) 0.114 (2.91) 0.076 (1.94) 0.076 (1.94) 0.076 (1.94) 0.114 (2.91) 3 8 10 16 13 16 13 14 11 10 8 7 5 6 3 1 8 9 10 11 7
rev. c 02/11 35 tfs757-764hg www.powerint.com part marking information ? hipertfs product family ? tfs series number ? package identifer h plastic esip-16b ? pin finish g halogen free and rohs compliant tfs 757 h g part ordering information part number option quantity pfs757hg tube 30 pfs758hg tube 30 pfs759hg tube 30 pfs760hg tube 30 pfs761hg tube 30 pfs762hg tube 30 pfs763hg tube 30 pfs764hg tube 30
revision notes date b initial release. 11/09/10 c updated absolute maximum ratings section. updated tfs759 i limit , figures 3, 25, 41, and package drawing. 02/11 for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or power integrationslly by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2011, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 1601/1610, tower 1, kerry everbright city no. 218 tianmu road west, shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokomana, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760

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